1. Field of the Invention
The present invention generally relates to electronic circuit packaging and, more particularly, to power distribution for single and multi-chip packages, especially packages including CMOS chips.
2. Description of the Prior Art
Recent advances in performance, integration density and manufacturing economy have made complementary metal-oxide-semiconductor (CMOS) designs the technology of choice for digital processing circuits in virtually all applications except where extreme switching speed approaching microwave frequencies is required. At the current time, a new generation of CMOS technology is introduced every twelve to eighteen months with a 100% increase in integration density and a 20%-30% increase in performance.
Scaling active elements such as transistors to smaller sizes and increased integration density and obtaining higher switching speeds has generally required reduced operating voltages and increased input and output (I/O) connection densities on the package. Each new generation of CMOS technology also represents about a 30% reduction in operating voltage and multiple voltages must be accommodated by I/O connections to allow communication and operation with past (or future) generation devices.
These trends lead to application specific integrated circuits (ASICS), memories, microprocessors and other types of integrated circuits which must include multiple drivers to provide voltages for signals communicated to other chips which operate at voltages different from the voltages at which the integrated circuits themselves are intended to principally operate. These multiple voltages, of course, require separate power distribution networks in the circuit package supporting the chip(s) which contain these drivers. At the same time, high clock speeds and switching frequencies must be maintained for increased numbers of devices which switch simultaneously. Current transients which are caused by core logic and I/O switching activity cause voltage fluctuations in the chip and the package power distribution network due to parasitic inductance in the package, resulting in so-called delta-I noise.
This delta-I noise not only affects on-chip circuits but also transmits through quiet off-chip drivers, and, combined with signal coupled noise and reflection noise, can propagate to receivers. This combined noise tends to increase while signal levels decrease with succeeding generations of technology; significantly reducing the signal-to-noise ratio (SNR) and leading to performance degradation and data integrity concerns, particularly in regard to memory read operations and dynamic logic circuits which are precharged prior to input signal evaluation.
It is therefore an object of the present invention to provide a power distribution arrangement for single and-or multi-chip packages with significantly reduced parasitic and loop-inductance and consequently reduced delta-I noise.
It is another object of the invention to provide an electronic integrated circuit package having an increased signal-to-noise ratio even when CMOS circuits operating at reduced voltages are included therein.
In order to accomplish these and other objects of the invention, an integrated circuit device and multi-layer connection structure forming a power distribution network for a plurality of voltages and ground are provided comprising alternating layers of patterned conductive layers and insulating layers, alternating patterned conductive layers being power distribution layers and signal layers, respectively, alternating power distribution layers being ground and voltage distribution layers, respectively, and vias selectively connecting selected conducting regions of the patterned conductive layers, wherein a voltage distribution layer is partitioned into respective areas for respective voltages that may appear in signal connections in an adjacent layer.